The present invention relates to a semiconductor memory element and a semiconductor device.
In recent years, flash memories which are introduced into a large number of apparatuses as the ones for storing programs or for storing data. The problem encountered with the flash memories is the price thereof. The price per capacity thereof is several or more fold higher as compared with other media such as hard disks, magneto-optic disks, and DVDs, resulting in a demand for cost reduction. The cost reduction can be achieved most effectively by a decrease in chip area. In contrast, there has been adopted in the prior art an approach of reducing the area of the memory cell. This is implemented by physically reducing the memory cell size due to miniaturization. One example of the memory cell size reduction due to miniaturization is described in H. Miwa et al. xe2x80x9cA 140 mm2 64 Mb AND Flash Memory with A 0.4 xcexcm Technologyxe2x80x9d IEEE, International Solid-State Circuit Conference 1996, p34-35 (1996). Alternatively, the so-called multi-level technology has come into actual use, which enables every memory cell to store two bits of information, thereby to effectually reduce the memory cell area per bit, or other approaches have been made. The prior art example of the multi-level memory is described in T. Jung et al., xe2x80x9cA 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applicationsxe2x80x9d IEEE International Solid-State Circuit Conference 1996, p32-33 (1996).
For ensuring the reliability, in a flash memory, scaling cannot be performed in the direction of thickness. Therefore, it is not possible to set the operation voltage at a lower level. Similarly, for ensuring the reliability, electron transfer must be performed through an oxide film formed by directly thermally oxidizing a silicon substrate. The oxide film is less susceptible to charge leakage. Accordingly, use of large positive and negative voltages is unavoidable. For this reason, the peripheral circuit, particularly, the power source occupies large area. As a result, the proportion of the area of the memory cells is reduced, leaving a problem that the chip area cannot be reduced even through miniaturization. The increase in cost due to a reduction in proportion of the memory cell area presents a large problem for a flash-embeded logic circuit for incorporation into an apparatus, or the like.
An object of the present invention is to provide a memory element configuration whereby the required voltages are few in kind, and the voltage is low, while ensuring the reliability. By using the memory element, it becomes possible to simplify the configurations of the peripheral circuits of a semiconductor memory device, and thereby to reduce the chip area. Namely, it becomes possible to provide a method for implementing a low cost semiconductor memory device.
The present invention is characterized in the following respects. Charges are not stored in a single region in a memory cell as in the prior art, but stored in a plurality of dispersed regions. In consequence, high reliability is implemented. The operation mode is simplified by performing electron transfer through not only the oxide film obtained by directly thermally oxidizing a high reliability silicon substrate but also another oxide film obtained from deposition by CVD (Chemical Vapor Deposition), or the like. As a result, the cost reduction of the semiconductor memory device is achieved.
More specifically, a semiconductor device in accordance with a typical embodiment of the present invention is mainly made up of semiconductor memory elements, each of which has:
a source region,
a drain region,
a channel region made of a semiconductor,
the source region and the drain region being connected by the channel region,
a gate electrode made of a metal or a semiconductor for controlling the electric potential of the channel region, and
a plurality of charge storage regions in the vicinity of the channel region,
wherein the electric potential to be applied to the gate electrode upon writing of data and the electric potential to be applied to the gate electrode upon erasing of data have the same polarity.
Other means, objects, and features of the present invention will become apparent from the following embodiments.